Methods and systems for programmable memory using silicided poly-silicon fuses

ABSTRACT

The present invention is directed to methods and systems for evaluating one-time programmable memory cells. A threshold current is applied to a resistive circuit, thereby generating a threshold voltage. A read current is applied to a first memory cell, thereby generating a memory cell voltage. The memory cell voltage is compared to the threshold voltage, thereby determining the state of the memory cell. In a further embodiment of the invention, a second threshold voltage is generated and compared the memory cell voltage, thereby verifying the state of the memory cell. The threshold current is optionally a substantial replica of said read current. The threshold current is optionally a proportional substantial replica of said read current. In an embodiment, the resistive circuit includes a second memory cell, which can be programmed or unprogrammed. The second memory cell is optionally arranged to average the memory cell resistance.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional PatentApplication No. 60/377,238, filed May 3, 2002, which is incorporated byreference herein in its entirety.

[0002] This application is a continuation-in-part of a U.S. patentapplication Ser. No. 10/115,013, filed Apr. 4, 2002, to Akira et al.which is incorporated by reference herein in its entirety.

BACKGROUND OF THE INVENTION

[0003] 1. Field of the Invention

[0004] The present invention is directed to semiconductor fuses andsystems and methods for programming semiconductor fuses.

[0005] 2. Background Art

[0006] In the field of data storage, there are two main types of storageelements. The first type is volatile memory that has the informationstored in a particular storage element, and the information is lost theinstant the power is removed from a circuit. The second type is anonvolatile storage element, in which the information is preserved evenwith the power removed. In regards to the nonvolatile storage elements,some designs allow multiple programming, while other designs allowone-time programming. Typically, the manufacturing techniques used toform nonvolatile memories are quite different from a standard logicprocess. The non-volatile memory manufacturing techniques increase thecomplexity and chip size.

[0007] Complimentary Metal Oxide Semiconductor (CMOS) technology is theintegration of both NMOS and PMOS transistors on a silicon substrate(collectively know as MOS field effect transistors, or MOSFETs). TheNMOS transistor consists of a N-type doped polysilicon gate, a channelconduction region, and source/drain regions formed by diffusion ofN-type dopants in the silicon substrate. The channel region separatesthe source from the drain in the lateral direction, whereas a layer ofdielectric material that prevents electrical current flow separates thepolysilicon gate from the channel. Similarly, the architecture is thesame for the PMOS transistor, except a P-type dopant is used.

[0008] The dielectric material separating the polysilicon gate from thechannel region, henceforth referred to as the gate oxide, usuallyconsists of the thermally grown silicon dioxide (SiO₂) material thatleaks very little current through a mechanism, which is calledFowler-Nordheim tunneling under voltage stress. Thin oxides that allowdirect tunneling current behave differently than thicker oxides, whichexhibit Fowler-Nordheim tunneling.

[0009] Conventional semiconductor fuses are capable of being programmedthrough application of a large current source to its poly-silicon layer.Such application of current causes the poly-silicon layer of the fuse tomelt. Molten poly-silicon agglomerates towards both ends of the fuse.One of the disadvantages of this method is that the programmed fuse isprone to contamination through the passivation window opening.

[0010] Furthermore, the need for high voltages to be internallygenerated to create such high currents can impact reliability of theprogrammed fuse and integrity of underlying oxide layers in sub-micronCMOS processing, which cannot tolerate high programming voltages. Due tothis reliability hazard, the unpredictability of post-programmingresistance of the fuse also increases.

[0011] Therefore, there is a need for methods and systems that arecapable of providing a reliable non-volatile one-time programming memoryelement. One-time programmable memory element should be compatible withsub-micron CMOS processing and provide predictable post programmingresistance in the fuse.

BRIEF SUMMARY OF THE INVENTION

[0012] The present invention relates to systems and methods forprogramming, reading and verification of a one-time programmable memoryelement. The one-time programmable memory element includes a memory coresystem and a digital interface that supplies input reference signals tothe memory core system.

[0013] The memory core system includes a fuse array having a pluralityof memory cells. The memory core system optionally includes one or moreof the following: an internal timing generator, an address decoder, acurrent reference generator, a verification circuit, a sense amplifier,and a digital sequencer. Each memory cell can include a polycide fuseand a control circuit. The memory core system operates in three modes:programming mode, reading mode and verification mode. The memory coresystem is capable of automatic and manual switching between the threemodes.

[0014] During the programming mode, the internal timing generatorreceives an input digital signal from the digital interface. Theinternal timing generator generates address signals. The address signalsalong with an input signal received by the address decoder are decodedinto an address defining a memory cell within the fuse array. In anembodiment, the memory cells in the fuse array are arranged in arow-column matrix configuration. The address signals define a particularrow and column of the memory cell for programming.

[0015] Once the memory cell is selected, the verification circuitverifies that the unprogrammed memory cell voltage is below verificationcircuit pre-programmed threshold voltage (in other words, theunprogrammed memory cell is a “good quality” unprogrammed memory cell).The current reference generator applies a current to the unprogrammedselected memory cell generating a particular voltage. This voltage iscompared with the pre-programming threshold voltage generated by theverification circuit. If the voltage is less than the threshold voltage,then the selected memory cell is a “good quality” memory cell andprogramming of the memory cell begins. If the voltage is not less thanthe threshold voltage, then another memory cell is selected.

[0016] During the programming mode, a constant amount of current isapplied to the selected memory cell over time. The current burns anopening in a polysilicon layer of the polycide fuse, thus, creating ahigh resistance path.

[0017] During a reading mode, the memory core system checks whether theselected memory cell was programmed. The current reference generatorapplies a current to the programmed memory cell generating a voltage.This voltage is compared against a reading threshold voltage generatedby the verification circuit. If the two voltages are comparable, theselected memory cell is declared programmed.

[0018] The verification mode verifies that a programmed memory cellvoltage is above a post-programming threshold voltage (in other words,the programmed memory cell is a “good quality” memory cell). This issimilar to the pre-programming verification mode. The current referencegenerator applies current to the programmed memory cell generating avoltage. This voltage is compared against the post-programming thresholdvoltage generated by the verification circuit. If the voltage is greaterthan the threshold voltage, then the programmed memory cell is a “goodquality” programmed memory cell. If not, then another memory cell mustbe selected for programming.

[0019] During the verification mode, the unprogrammed and programmedmemory cell are compared against threshold voltages representing maximumand minimum threshold voltages generated by the memory core system,respectively. The verification mode's maximum and minimum thresholdvoltages provide a better threshold voltage standard as compared withthe reading threshold voltage. In an embodiment, the reading thresholdvoltage is between the maximum pre-programming threshold voltage and theminimum post-programming threshold voltage. As would be understood byone having ordinary skill in the art, the memory cell voltage generatedduring the reading mode does not have to match the reading thresholdvoltage exactly. However, during the pre-programming verification mode,the unprogrammed fuse voltage must be less than or equal to the maximumpre-programming threshold voltage, if the unprogrammed fuse is to passas a “good quality” unprogrammed fuse. Also, during the post-programmingverification mode, the programmed fuse voltage must be greater than orequal to the minimum post-programming threshold voltage, if theprogrammed fuse is to pass as a “good quality” programmed fuse. In otherwords, the maximum pre-programming threshold voltage and the minimumpost-programming threshold voltage can be purposefully skewed togenerate appropriate voltage threshold against which the unprogrammedand programmed fuses can be compared to insure their “good quality”.

[0020] Further embodiments, features, and advantages of the presentinventions, as well as the structure and operation of the variousembodiments of the present invention, are described in detail below withreference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES

[0021] The accompanying drawings, which are incorporated herein and formpart of the specification, illustrate the present invention and,together with the description, further serve to explain the principlesof the invention and to enable a person skilled in the relevant art(s)to make and use the invention.

[0022]FIG. 1 is a block diagram of a one-time programmable elementmemory including a one-time programmable memory element core, accordingto the present invention.

[0023]FIG. 2 is a block diagram of the one-time programmable elementmemory core according to the present invention.

[0024]FIG. 3a is a block diagram of a conventional system forprogramming a memory cell.

[0025]FIG. 3b is a block diagram of a system for programming a memorycell, according to the present invention.

[0026]FIG. 3c is a flowchart diagram illustrating a method of currentapplication to a memory cell, according to the present invention.

[0027]FIG. 4 is a block diagram of an example address decoder of theone-time programmable element memory core as shown in FIG. 2.

[0028]FIG. 5a is a block diagram of an example internal timing generatorcircuit of the one-time programmable element memory core as shown inFIG. 2.

[0029]FIG. 5b is a timing diagram corresponding to an internal timinggenerator circuit shown in FIG. 5a, according to the present invention.

[0030]FIG. 6 is a block diagram of an example fuse array row-columnmatrix arrangement of the one-time programmable element memory core asshown in FIG. 2.

[0031]FIG. 7a is a top view of an example fuse in a memory cell.

[0032]FIG. 7b is a cross-sectional view of the example fuse in thememory cell shown in FIG. 7a.

[0033]FIG. 8a is a top view of another embodiment of a fuse in thememory cell.

[0034]FIG. 8b is a cross-sectional view of the fuse in the memory cellshown in FIG. 8a.

[0035]FIG. 9a is flow chart diagram illustrating a method forprogramming a one-time programmable element memory core.

[0036]FIG. 9b is a flow chart diagram illustrating a method forselecting a memory cell during the programming method of FIG. 9a.

[0037]FIG. 9c is a flow chart diagram illustrating a method forverifying a memory cell step during the programming method of FIG. 9a.

[0038]FIG. 9d is a flow chart diagram illustrating a method for applyinga current to a memory cell during the programming method of FIG. 9a.

[0039]FIG. 9e is a flow chart diagram illustrating an application of theone-time programmable element memory shown in FIG. 1.

[0040]FIG. 10 is a block diagram of an example verification circuit ofthe one-time programmable element memory core as shown in FIG. 2.

[0041]FIG. 11 is a Gaussian distribution of memory cell voltagesgenerated during reading and verification modes of the one-timeprogrammable element memory core shown in FIG. 2.

[0042]FIG. 12a is flow chart diagram illustrating a method for reading aone-time programmable element memory core.

[0043]FIG. 12b is a flow chart diagram illustrating a method forgenerating a threshold voltage during the reading method of FIG. 12a.

[0044]FIG. 13a is flow chart diagram illustrating a method for verifyingan unprogrammed one-time programmable element memory core.

[0045]FIG. 13b is flow chart diagram illustrating a method for verifyinga programmed one-time programmable element memory core.

[0046]FIG. 13c is a flow chart diagram illustrating a method forgenerating a pre-programming threshold voltage during the verificationmode method of FIG. 13a.

[0047]FIG. 13d is a flow chart diagram illustrating a method forgenerating a post-programming threshold voltage during the verificationmode method of FIG. 13b.

[0048]FIG. 13e is a flow chart diagram illustrating independentinitiation of a verification mode shown in FIGS. 13a-13 d, according tothe present invention.

[0049]FIG. 14a illustrates a top view of a one-time programmable elementmemory cell, according to the present invention.

[0050]FIG. 14b illustrates atop view of another one-time programmableelement memory cell, according to the present invention.

[0051]FIG. 14c is a cross-sectional view of an unprogrammed memory cell,according to the present invention.

[0052]FIG. 14d is a cross-section view of a programmed memory cell,according to the present invention.

[0053]FIG. 15 illustrates an example embodiment of a sense amplificationcircuit.

[0054] The present invention is described with reference to theaccompanying drawings. In the drawings, like reference numbers indicateidentical or functionally similar elements. Additionally, the leftmostdigit of a reference number identifies the drawing in which thereference number first appears.

DETAILED DESCRIPTION OF THE INVENTION

[0055] Table of Contents. 1. Introduction. 2. One-Time Programmable(OTP) Memory Element - System Structure. a. OTP Memory Core. b.Row-column Matrix Memory Array Scheme. c. Address Decoder. d. InternalTiming Generator. e. Verification Circuit. f. PMOS Diode. 3. OTP MemoryElement in - System Operation. a. Programming Mode. b. Reading Mode. c.Verification mode. 4. Poly-Si Fuse Design. 5. Conclusion.

[0056] While the present invention is described herein with reference toillustrative embodiments for particular applications, it should beunderstood that the invention is not limited thereto. Those skilled inthe art with access to the teachings provided herein will recognizeadditional modifications, applications, and embodiments within the scopethereof and additional fields in which the present invention would be ofutility.

[0057] 1. Introduction.

[0058] The present invention relates to semiconductor programmableelements. In particular, the present invention is directed to a one-timeprogrammable (“OTP”) memory element. OTP memory elements are alsoreferred to herein as semiconductor fuses. Semiconductor fuses are used,for example, in non-volatile memory storage applications. The presentinvention also relates to poly-silicon fuses.

[0059] The semiconductor fuse is a device that provides a relatively lowresistance when it is not programmed, and relatively high resistancewhen it is programmed. Conventional poly-silicon fuses are fabricatedwith a window opening, also known as fuse window, in a passivation layer(e.g., polyamide). The poly-silicon fuse can be P+doped, N+doped, orundoped. When a sufficiently high current is passed through the fuse,the fuse is heated up beyond its melting point. Therefore, a portion ofa poly-silicon fuse under the fuse window will melt such that the moltenpoly-silicon material agglomerates towards one or both ends of the fuse.

[0060] There are several disadvantages of the above fusing method. Theprogrammed fuse is prone to contamination through the passivation windowopening. Secondly, a relatively high voltage is required to generate thehigh current necessary to melt poly-silicon fuse strips reliably. Suchhigh voltage is not suitable for deep sub-micron CMOS processes (e.g.,0.13 μm CMOS processing, which tolerates a maximum of 2.5 V to 3.3 V).To internally program such fuse in 0.13 μm CMOS process technologyconventionally, use of internal voltage multipliers is required. Theinternal voltage multipliers can cause unintentional transistor gateoxide breakdown, if voltage multiplication becomes excessive.

[0061] Another disadvantage of conventional fusing is in the fabricationprocess. The fabrication process requires a masking step to create thefuse window, and a post-programming oxidation step to cover the fusewindow. This means that the programming of the fuse can only be doneduring the wafer making stage. Therefore, the end users of the finalpackaged product containing such a fuse are unable to program the fuses.Yet another problem encountered in conventional fuses concernsprogramming reliability. Although a programmed or unprogrammed fusegenerates an apparently proper voltage during a read cycle, thegenerated voltage may be near a reading threshold voltage. Changes inenvironmental conditions, changes in the fuse over time, and or changesin supply voltage and/or ground levels, may however, result in aprogrammed or unprogrammed fuse generating a voltage that no longermeets the reading threshold.

[0062]FIGS. 7a and 7 b illustrate an example fuse 700, as describedabove. FIG. 7a illustrates a top view of the fuse 700. FIG. 7billustrates a cross-sectional view of the fuse 700 taken at line A ofFIG. 7a.

[0063] Referring to FIG. 7a, fuse 700 includes a fuse window 710,polyamide layers 720 and a poly-silicon layer 750. Poly-silicon layer750 can be P+doped, N+doped, or undoped. An application of high voltageto the fuse generates current necessary to melt poly-silicon layer 750.The current necessary to melt poly-silicon layer 750 passes through fusewindow 710.

[0064]FIG. 7b illustrates fuse window 710, polyamide layer 720, metallayer 730 and oxide layer 740, poly-silicon layer 750 and an oxide layer760. Application of current to fuse 700 melts poly-silicon layer 750 toform a high resistance path through oxide layer 760.

[0065]FIGS. 8a and 8 b illustrate another example fuse 800. FIG. 8aillustrates a top view of the fuse 800. FIG. 8b illustrates a crosssectional view of the fuse 800 taken at line B. Fuse 800 eliminates theneed to have a fuse window and allows fuse programming to be done atrelatively low voltage in an embedded environment. Fuse 800 is sometimesreferred to as a silicided poly-silicon fuse or a polycide fuse.

[0066]FIG. 8b illustrates fuse 800 having polyamide layer 810 (alsoreferred to as passivation layer), metal layer 830 and oxide layer 840,silicide layer 850, poly-silicon layer 860, and oxide layers 870, 880and 890. Normally, metal layers 830 conduct through poly-silicon layer860 and silicide layer 850. Application of current to fuse 800 (i.e., tometal layer 830) melts silicide layer 850 to disrupt the conductive paththrough the poly-silicon layer 860 and silicide layer 850.

[0067] As compared to fuse 700, fuse 800 does not suffer from therelatively high programming voltage issue discussed above, because amuch lower voltage is needed to generate a lower current for programmingcompared to fuse 700. However, both fuses 700 and 800 do not address theoperational reliability in the fuse programming. To ensure that fusescan be used reliably in the actual non-volatile memory application,methods and systems to program, read and verify these fuses is needed,wherein verification uses thresholds that are more demanding than readthresholds.

[0068] 2. One-Time Programmable (OTP) Memory Element—System Structure.

[0069] a. OTP Memory Core.

[0070]FIG. 1 is a block diagram of a one-time programmable (“OTP”)element memory 100. OTP element memory 100 includes an OTP elementmemory core 120 and a digital interface 130. OTP element memory core 120is coupled to digital interface 130. Digital interface 130 performsmemory address generation, program access control, error correction bybit-remapping and manufacturing testing. Digital interface 130 alsoprovides control data input to OTP element memory core 120.

[0071]FIG. 2 illustrates OTP element memory core 120 in more detail. OTPelement memory core 120 includes a PMOS diode 210, a current referencegenerator 220, fuse array 230, an address decoder 240, a sense amplifier250, verification circuits 260, an internal timing generator 270 and adigital sequencer 280.

[0072] PMOS diode 210 is coupled to fuse array 230. PMOS diode 210generates a voltage VDRIVE 213 during an OTP element memory core 120programming mode. This voltage is used to bias a gate of a currentsource transistor in an activated memory cell in fuse array 230 duringOTP element memory core 120 programming mode.

[0073] Current reference generator 220 is coupled to fuse array 230 andverification circuits 260 and verification circuits 260. Currentreference generator 220 provides currents to fuse array 230 during OTPelement memory core 120 reading mode and verification mode. The currentsare provided to activated or enabled memory cells in order to generateread voltages. Current reference generator 220 also supplies a currentV_(ref) _(—) I_(out) 221 to the verification circuits 260. V_(ref) _(—)I_(out) 221 is an exact replica of an IFEED signal 222 (supplied tocurrent reference generator 220), so that the verification circuits 260can generate a VREF_OUT signal 264 that tracks RDLINE signal 231voltages under changing supply conditions. A memory cell is activated orenabled when it is selected for programming or reading in OTP elementmemory core 120. The read voltages indicate status of a memory cell infuse array 230 after OTP element memory core 120 programming mode orduring reading/verification modes. Current reference generator 220 alsosupplies current to sense amplifier 250.

[0074] Fuse array 230 includes a plurality of memory cells. In anembodiment, memory cells are arranged in a row-column matrixarrangement. Each memory cell can include a polycide fuse and a controlcircuit. In an embodiment, there can be 8 rows of 32-bit (columns) ofmemory cells. This provides 256 bits of memory represented by memorycells in fuse array 230. As would be understood by one skilled in therelevant art, other arrangements of memory cells within fuse array 230are possible.

[0075] Address decoder 240 receives signals ROW_CLK 271, COL_CLK 272 andADDR_CLK 273 from internal timing generator 270. In an embodiment,ROW_CLK 271, COL_CLK 272, and ADDR_CLK 273 are timing signals. Thesetiming signals help to ensure that 8-bit input address signals 245 areproperly latched on and stable in fuse array 230 before programming,reading or verification modes start. Based on these signals, addressdecoder 240 generates control signals that enable or activate a memorycell or fuse in fuse array 230.

[0076] Sense amplifier 250 is coupled to verification circuits 260 andfuse array 230. Sense amplifier 250 determines a state (e.g., programmedor unprogrammed) of the activated or enabled memory cell in fuse array230. Sense amplifier 250 compares voltage RDLINE 231 generated by anenabled memory cell in fuse array 230 with a reference voltage VREF_OUT264 generated by verification circuit 260. At least one sense amplifieris needed to operate the system. In an embodiment, if there are eightmemory cells present in fuse array 230, there can be sense amplifier 250coupled to each of the eight memory cells in fuse arrays 230. In otherwords, because there are eight sense amplifiers 250 and RDLINE 231 is an8-bit bus so that eight memory cells can be read at one time to form aone byte (one byte equals to eight bits).

[0077] Verification circuits 260 are coupled to address decoder 240, andsense amplifier 250. Verification circuits 260 receive input digitalsignals 261 and 262, which are provided by digital interface 130 (notshown in FIG. 2). Verification circuits 260 provide one or morethreshold voltages based on input digital signals 261 and 262. Thethreshold voltages are provided to the sense amplifier 250 for useverifying a status of a memory cell in fuse array 230 duringprogramming, reading and/or verification modes.

[0078] Internal timing generator 270 is coupled to address decoder 240.Internal timing generator 270 controls timing for a fuse programmingprocess (described below). Internal timing generator 270 ensures thatthe fuses in fuse array 230 are provided with a consistent current forprogramming over time. Internal timing generator 270 also ensures thatthe fuses in fuse array 230 are programmed with suitable repeatability.

[0079] Digital sequencer 280 times programming, reading and verifyingcycles of OTP element memory core 120. This ensures that ample time isgiven for each mode (programming, reading, and verification) to completebefore allowing for the next mode to proceed. Digital sequencer 280 alsore-times input digital signals from digital interface 130. Digitalsequencer 280 times an actual memory cell programming period and apost-programming verification mode. This ensures that only a programmedmemory cell is a “good quality” programmed memory cell. In anembodiment, the term “good quality”, when used in reference to anunprogrammed memory cell, means that the unprogrammed memory cell has alow resistance and generates a low voltage, when a current is applied toit. In alternative embodiment, the term “good quality”, when used inreference to a programmed memory cell means that a programmed memorycell has a high resistance and generates a high voltage, when a currentis applied to it.

[0080] The following is a detailed description of the components andfunctions of OTP element memory core 120. As would be understood by oneskilled in the relevant art, the OTP element memory core 120 is notlimited to the components described herein.

[0081] b. Row-column Matrix Memory Array Scheme.

[0082]FIG. 6 illustrates an example of row-column matrix embodiment ofthe fuse array 230. In the embodiment of FIG. 6, the fuse array 230includes a plurality of fuses 601(a,b,c,d,e,f,g,h).

[0083] Input signals COL 241 and WRITE_ROW 242 select a memory cell orfuse 601 for programming. For example, COL 241 and WRITE_ROW 242 selectfuse 601 a. When fuse 601 a is selected, OTP element memory core 120 canprogram, read and/or verify fuse 601 a. During the programming mode, forexample, PMOS diode 210 (as shown in FIG. 2) applies a relativelyconstant current over a period of time to fuse 601 a by providing aVDRIVE voltage signal 213 via a connector 213 a in a current mirrorconfiguration. The current applied through this current mirrorconfiguration melts a poly-silicon layer of the fuse 601 a. By applyinga relatively constant current to fuse 601 a, an opening is created inthe fuse 601 a's silicide and/or poly-silicon layers. Therefore, fuse601 a now has a relatively high resistance as compared to anunprogrammed fuse 601 a, which has a relatively low resistance. A methodof current application to fuse 601, during the programming mode, isdescribed below.

[0084] During the reading mode, current reference generator 220 appliesa read current IFEED 222 via a connector 222 a to fuse 601 a. When fuse601 a has been programmed, read current IFEED 222 via connector 222 aencounters resistance of programmed fuse 601 a. When the reading currentis applied to programmed fuse 601 a, a fuse voltage is generated. Thefuse voltage depends on the resistance of the fuse. The fuse voltage ismonitored via signal line RDLINE 231 via a connector 231 a. The fusevoltage is fed into sense amplifier 250 via RDLINE 231. Based on voltageRDLINE 231, sense amplifier 250 determines whether fuse 601 a isprogrammed or not.

[0085]FIG. 6 shows an example embodiment of a row-column matrixconfiguration used for a 256-bit memory cell bank. This allows for anefficient addressing and memory read and write access, because the sameset of address lines (COL 241 and WRITE_ROW 242) and read lines (RDLINE231) is shared among multiple fuses 601. Such sharing of COL 241 andRDLINE 231 allows a whole column of 8-bit cells to be selected togetherduring a single read access, hence, shortening the total read time. Thisresults in minimum routing of signals and allows more cells to be packedin a dense fashion without significant timing delay spreads. As would beunderstood by one having ordinary skill in the art, other embodiments offuse array 230 are possible.

[0086] c. Address Decoder.

[0087]FIG. 4 is a block diagram of address decoder 240. Address decoder240 includes a COL_DECODE block 410 and ROW_DECODE block 420. Addressdecoder 240 receives a plurality of addressing signals ROW_CLK 271,COL_CLK 272 and ADDR_CLK 273 from internal timing generator 270. Also,address decoder 240 receives input address signal 245 from digitalinterface 130. In an embodiment, input address signal 245 is an 8-bitdigital signal. Input address signal 245 represents eight bits ofaddressing that are combined with addressing signals from internaltiming generator 270. Furthermore, input address signal 245 correspondsto the fuse array 230 row-column matrix embodiment shown in FIG. 6 (asshown in FIG. 6, there are eight rows of 32-bit columns).

[0088] Addressing signals ROW_CLK 271, COL_CLK 272 and ADDR_CLK 273along with input address signal 245 are decoded by COL_DECODE block 410and ROW_DECODE block 420. Resulting output signals COL 241, WRITE_ROW242 and READ_ROW 243 define an address of a memory cell within fusearray 230.

[0089] COL 241 represents 32 column select bits. WRITE_ROW 242represents eight row select bits. COL 241 and WRITE_ROW 242 select afuse in the fuse array block 230 for programming mode. READ_ROW 243signal represents eight row select bits for reading and verifying modes(described below).

[0090] As would be understood by one having an ordinary skill in theart, other embodiments of selecting a fuse in the fuse array block 230are possible. The address decoder 240 of OTP element memory core 120 isnot limited to the embodiment shown in FIG. 4.

[0091] d. Internal Timing Generator.

[0092]FIG. 5a is a block diagram of internal timing generator 270.Internal timing generator 270 includes an ADDR_CLK signal generator 510,a ROW_CLK signal generator 520 and a COL_CLK signal generator 530.

[0093] Internal timing generator 270 receives an input signal CLK 275from digital interface 130. The circuitry of internal timing generator270 converts input signal CLK 275 through logic operations into COL_CLKsignal 271, ROW_CLK signal 272 and ADDR_CLK signal 273. COL_CLK 271,ROW_CLK 272 and ADDR_CLK 273 are supplied to address decoder 240, whichselects a fuse from fuse array block 230.

[0094] In an embodiment, internal timing generator 270 provides a highlyrepeatable way of selecting a memory cell within fuse array block 230 byproviding sufficient time margins for programming, reading andverification modes. This makes operation of OTP element memory core 120more robust against process, temperature and input signal supplyvariations. Furthermore, internal timing generator 270 ensures thatprogramming mode and reading mode of a fuse in fuse array 230 are donewith minimal disturbance. This is shown in a timing diagram in FIG. 5b.

[0095] Referring to FIG. 5b, a time interval 571 in ADDR_CLK signal 273time line corresponds to address input signal 245 being received byaddress decoder 240. This triggers COL signal 241 to select and enable acolumn of cells in fuse array 230 during a time interval 572 on COL_CLKsignal 271 time line. Fuse programming begins at a time 573 on ROW_CLKsignal 272 time line by having a programming current flow into aselected cell. The selected cell is programmed upon activation ofWRITE_ROW signal 242 during a time interval 574 on ROW_CLK signal 272time line.

[0096] e. Verification Circuit.

[0097]FIG. 10 is a block diagram of verification circuit 260. FIG. 11 isa diagram illustrating Gaussian distributions of fuse voltages andthreshold voltages for a plurality of memory cells in fuse array 230 inverification mode.

[0098] Verification circuit 260 implements reading and verifying ofmemory cells from fuse array 230. During the verification mode, theunprogrammed and programmed memory cells are compared against thresholdvoltages representing maximum and minimum verification thresholdvoltages generated by the memory core system, respectively. The maximumand minimum verification threshold voltages provide a more accuratethreshold voltage standard as compared to the reading threshold voltage.In an embodiment, the maximum and minimum verification thresholdvoltages can be purposefully skewed. This means that maximum and minimumverification threshold voltages would represent maximum and minimumallowed thresholds, respectively. In another embodiment, the readingthreshold voltage is between the maximum pre-programming thresholdvoltage and the minimum post-programming threshold voltage. As would beunderstood by one having ordinary skill in the art, the memory cellvoltage generated during the reading mode does not have to match thereading threshold voltage exactly.

[0099] However, during the pre-programming verification mode, theunprogrammed fuse voltage must be less than or equal to the maximumpre-programming verification threshold voltage, if the unprogrammed fuseis to pass as a “good quality” unprogrammed fuse. In an embodiment, theterm “good quality”, when used in reference to an unprogrammed fuse,means that the unprogrammed fuse has a low resistance and generates alow voltage when a current is applied to it. In another embodiment, theterm “good quality”, when used in reference to a programmed fuse meansthat a programmed fuse has a high resistance and generates a highvoltage, when a current is applied to it. The pre-programmingverification mode is useful during production tests to ensure that thememory cells are of “good quality” before delivery to customers.

[0100] During the post-programming verification mode, the programmedfuse voltage must be greater than or equal to the minimumpost-programming threshold voltage, if the programmed fuse is to pass asa “good quality” programmed fuse. In other words, the maximumpre-programming threshold voltage and the minimum post-programmingthreshold voltage can be purposefully skewed to generate a maximum andminimum allowed voltage threshold against which the unprogrammed andprogrammed fuses can be compared to insure their “good quality”,respectively.

[0101] Verification circuit 260 includes a plurality of thresholdmodules 1021, 1022, and 1023, coupled to digital verification circuitry1005, and transistor switches 1006, 1007, and 1008. Threshold modules1021, 1022, and 1023 include one or more resistive circuits, such asunprogrammed and/or programmed fuses, in any of a variety ofconfigurations. A current V_(ref) _(—) L_(out) 212 is applied to thethreshold modules 1021, 1022 and 1023, thereby generating voltagethresholds V_(threshp), VT_READ, and V_(threshb), respectively. Thecurrent V_(ref) _(—) I_(out) 221 is a substantial replica of IFEEDcurrent 222 (not shown in FIG. 10).

[0102] Signals VERIFY 261 and DI 262 serve as digital inputs fromdigital interface 130 (as shown in FIG. 1). Signal READ_ROW 243 fromaddress decoder 240 (shown in FIG. 2) is another input signal to digitalverification circuitry 1005. These signals supply input signals todigital verification circuit 1005. Based on the input signals, digitalverification circuit 1005 generates voltage signals VERIFY_BLOWN 1012,READ_VREF 1013, and VERIFY_PREBLOWN 1014. Signals 1012, 1013 and 1014control transistor switches 1006, 1007, and 1008, respectively, toprovide one of the voltage thresholds at the output terminal VREF_OUT264, depending upon a mode of operation as described below.

[0103] During the verification mode of an unprogrammed fuse signalVERIFY_PREBLOWN 1014 applies to transistor switch 1008 to close it.Therefore, voltage signal V_(threshp) passes through transistor switch1008 to the output terminal VREF_OUT 264.

[0104] During the reading mode of a programmed or unprogrammed fuse,signal READ_VREF 1013 applies to transistor switch 1007 to close it.Therefore, signal VT_READ passes to the output terminal VREF_OUT 264 ofthe verification circuit 260.

[0105] During the verification mode of a programmed fuse, signalVERIFY_BLOWN 1012 is applied to transistor switch 1006 to close it.Therefore, signal V_(threshb) passes to the output terminal VREF_OUT 264of the verification circuit 260.

[0106]FIG. 11 shows fuse voltage distribution as compared againstthreshold voltages generated by threshold modules 1021, 1022, and 1023.Voltage V_(threshp) generated by threshold module 1023 corresponds tovoltage V_(threshp) 1114 in FIG. 11. Voltage VT_READ generated bythreshold module 1022 corresponds to voltage VT_READ 1113 in FIG. 11.Voltage V_(threshb) generated by threshold module 1021 corresponds tovoltage V_(threshb) 1112 in FIG. 11. As shown in the embodiment of FIG.11, V_(threshp) 1114 is less than VT_READ 1113 and VT_READ 1113 is lessthan V_(threshb) 1112. As would be understood by one having ordinaryskill in the art other reference voltage distributions are possible.

[0107] During the verification mode, one of transistor switches 1006 and1008 are switched on, depending on whether a programmed or anunprogrammed memory cell is being verified. Verification circuit 260 isused during pre-programming phase of the programming mode and duringpost-programming phase of the programming mode. In the pre-programmingphase, verification circuit 260 determines whether the selected memorycell 601 (as shown in FIG. 6) is a “good quality” memory cell.Verification circuit 260 applies a current to the unprogrammed memorycell 601 to generate a fuse voltage. The fuse voltage should be lowenough to pass the “good quality” cell standard (as described above).

[0108] In the post-programming phase, verification circuit 260determines whether the programmed memory cell 601 is a “good quality”programmed memory cell. Verification circuit 260 applies a current tothe programmed memory cell 601 to generate a fuse voltage. The fusevoltage should be high enough to pass the “good quality” programmed cellstandard (as described above).

[0109] In an embodiment, the threshold modules are implemented withfuses that can be similar to the fuses in the fuse array 230. Resistanceof each such fuse can vary. In an embodiment, fuses within the thresholdmodules are preferably arranged to average the resistance of the fuses.

[0110] In an embodiment, threshold modules 1021, 1022 and 1023 includean array of fuses connected in series-parallel arrangement. For example,threshold module 1021 is illustrated with eight unprogrammed fuses1041(a,b,c,d,e,f,g, h). Fuses 1041 a, 1041 b, 1041 c, and 1041 d areconnected in series. Fuses 1041 e, 1041 f, 1041 g, and 1041 h are alsoconnected in series. Series connected fuses 1041(a,b,c,d) are connectedin parallel to series connected fuses 1041(e,f,g,h). Such arrangement ofunprogrammed fuses 1041(a-h) provides an averaging of fuse resistances.Therefore, a final resistance of threshold module 1021 is$\begin{matrix}{\frac{1}{R_{1021}} = {\frac{1}{R_{1041a} + R_{1041b} + R_{1041c} + R_{1041d}} + \frac{1}{R_{1041e} + R_{1041f} + R_{1041g} + R_{1041h}}}} & (1)\end{matrix}$

[0111] If the resistance of each fuse 1014 is equal to R, then R₁₀₂₁ isequal to 2R. As would be understood by one having ordinary skill in theart, other embodiments of verification circuit 260 along with thresholdmodules 1021, 1022, and 1023 are possible. The threshold modules 1021,1022, and 1023 are not limited to the embodiment shown in FIG. 10. Therecan be any number of fuses and/or other resistive devices withinthreshold modules 1021, 1022, and 1023. Using fuses similar to the fuses601 and having V_(ref) _(—) I_(out) 221 substantially equal to IFEED 222provides advantages such as tracking of process, voltage and temperaturevariations.

[0112] Referring to FIG. 11, after the fuse has been programmed,verification circuit 260 confirms that it was programmed by enteringinto the verification mode. In the verification mode, current is appliedto programmed fuse 601 to generate the fuse voltage that will becompared against the V_(threshb) 1112 generated by signal verificationcircuit 260 at output terminal READ_VREF 264. When the fuse voltagegenerated by fuse 601 is greater than the V_(threshb) 1112, fuse 601 isconsidered programmed. If the fuse voltage generated by fuse 601 is lessthan V_(threshb) 1112, fuse 601 is considered unprogrammed.

[0113] In order to verify that an unprogrammed fuse in fuse array 230 isa “good quality” fuse, verification circuit 260 applies a current to theunprogrammed fuse to generate a pre-programmed voltage. Then,verification circuit 260 compares fuse's pre-programmed voltage tovoltage V_(threshp) 1114. Voltage V_(threshp) 1114 is generated bythreshold module 1023 of verification circuit 260, as described in FIG.10. Since the current applies to the unprogrammed fuse having a lowresistance, the fuse generates a low voltage signal. If the low voltagesignal is less than V_(threshp) 1114, then the fuse is a “good quality”fuse and can be programmed, if desired. If the low voltage signal ismore than V_(threshp) 1114, then the fuse is not a “good quality” fuseand will not be programmed (as described above).

[0114] In order to verify that the fuse was properly programmed,verification circuit 260 applies a current to the programmed fuse togenerate a post-programming voltage. Then, verification circuit 260compares the programmed fuse's post-programming voltage to voltageV_(threshb) 1112. Voltage V_(threshb) 1112 is generated by thresholdmodule 1021 of verification circuit 260. Since the current applied tothe programmed fuse has a high resistance, the fuse will generate a highvoltage signal. If the high voltage signal is greater than V_(threshb)1112, then the fuse is a “good quality” programmed fuse. If the highvoltage signal is less than the V_(threshb) 1112, then the programmedfuse is not a “good quality” programmed fuse. In other words, theprogrammed fuse passes the verification test when its fuse voltage isgreater than V_(threshb) 1112. If the fuse voltage is less thanV_(threshb) 1112 then the programmed fuse does not pass the verificationtest. Note that this verification test/mode can be either initiatedautomatically after a fuse is programmed or it can be initiatedindependently.

[0115] Gaussian distribution 1100 illustrates unprogrammed fuse voltagedistribution curve 1101 and post-programmed fuse distribution curve1102. Curve 1101 and curve 1102 represent fuse voltages for theplurality of fuses within fuse array 230 of FIG. 2.

[0116] The following Table 1 summarizes concepts described above inconjunction with FIGS. 10 and 11 with respect to reading andverification modes. Table 1. Verification and Reading modes to checkfuse quality and normal read back, respectively (Logical HIGH indicatespresence of a signal; logical LOW indicates absence of signal). VERI-Resulting DI FY VREF_OUT Fuse Pass Mode 262 261 264 CriteriaVERIFY_BLOWN HIGH HIGH V_(threshb) 1112 Fuse 1012 Voltage ≧ V_(threshb)READ_VREF N/A LOW VT_READ N/A: 1013 1113 READ_VREF is used for normalmemory read cycle. Fuse Voltage > VT_READ implies fuse memory state isHIGH. Fuse Voltage < VT_READ implies fuse memory state is LOW.VERIFY_PRE- LOW HIGH V_(threshp) 1114 Fuse Voltage ≦ BLOWN 1014V_(threshp)

[0117] Referring to the first row of Table 1, during the verification ofa programmed memory cell the current is applied to the programmed memorycell based on digital input signals DI 262 and VERIFY 261 from digitalinterface 130. As a result, the programmed memory cell generates a fusevoltage. The fuse voltage should be relatively large, because memorycell is programmed and has a high resistance. The fuse voltage iscompared against V_(threshb) 1112. If the fuse voltage is greater thanor equal to V_(threshb) 1112, then the programmed memory cell passes theverification test, as indicated in Table 1.

[0118] During the verification of an unprogrammed memory cell a currentis applied to the unprogrammed memory cell. As a result, theunprogrammed memory cell generates a fuse voltage. The fuse voltageshould be relatively small, because the memory cell is not programmedand has a low resistance. The fuse voltage is compared againstV_(threshp) 1114. If the fuse voltage is less than or equal toV_(threshp) 1114, then the programmed memory is a “good quality” memorycell, i.e., passes the verification test for unprogrammed memory cell,as indicated in the third row of Table 1.

[0119] Referring to the second row of Table 1, during the reading mode,the verification circuit 260 generates voltage VT_READ 1113. In thereading mode, the current is applied to a programmed memory cell togenerate a voltage. That voltage is compared against VT_READ 1113. Asindicated in Table 1, if the programmed memory cell generates a voltagethat is above VT_READ 1113, then the memory cell is programmed. If theprogrammed memory cell generates a voltage that is below VT_READ 1113,then the memory cell is not programmed.

[0120] The verification mode ensures that programmed and unprogrammedmemory cells generate voltages that are well above or below the readingthreshold voltages, respectively. This helps to ensure that a “goodquality” memory cell is selected for programming and that a programmedmemory cell passes the verification test. In other words, theverification mode ensures that the selected memory cell retains all itsqualities before and after programming regardless of time, temperatureand other surrounding conditions. The verification circuit generates aset of more accurate threshold voltages against which fuse voltages arecompared in appropriate modes. When fuse voltages fall within limits setby the threshold voltage, the fuse is assured of its good quality.

[0121] f. PMOS Diode.

[0122]FIG. 3a is a block diagram of a fuse programming system 300 forprogramming fuse 601. FIG. 3b is a block diagram of a fuse programmingsystem 310 for programming fuse 601, according to an embodiment of thepresent invention.

[0123] In FIG. 3a, the fuse programming system 300 includes a transistorswitch M0 303, fuses selection circuit 301 and a reading circuit 302.Power supply terminals 211 and 212 apply current to fuse programmingsystem 300. Signals COL 241 and WRITE_ROW 242 originally select fuse 601for programming via fuse selection circuit 301. Fuse 601 is coupledbetween power supply terminals 211 and 212. Once fuse 601 is selected, aprogramming current is applied via transistor M0 303. Application ofprogramming current closes transistor M0 303, allowing the programmingcurrent to pass through to fuse 601. The programming current passesthrough fuse 601 from power supply terminal 211 to the ground 212. Suchapplication of current melts the fuse's poly-silicon/silicide layer. Inconventional systems, the programming current is relatively large, whichrenders the molten poly-silicon layer unstable. This means that thepoly-silicon may reseal itself and return the fuse to the initialunprogrammed state, or sometime in between. Also, the programmingvoltage applied to the fuse to program it is relatively high for the0.13 μm CMOS process technology. Therefore, there is a need for animproved methods and systems for programming fuses.

[0124]FIG. 3b is a block diagram of an improved fuse programming system310 for programming fuse 601. System 310 includes PMOS diode 210, fuseselection circuit 301, transistors M5 315, M4 316, and reading circuit302. Transistor M0 303 forms a current mirror configuration with PMOSdiode 210. PMOS diode 210 includes a current source transistor M7 312and a resistance R 314.

[0125] System 310 includes a current mirror configuration involvingtransistors M7 312 and M0 303. System 310 applies a constant amount ofcurrent, through the current mirror configuration, to fuse 601. Theamount of current is determined based on the voltages applied via powersupply terminals 211 and 212, as well as a voltage, VGSP_CORE 313.VGSP_CORE voltage 313 is used to bias the gate of current sourcetransistor M7 312, when fuse 601 is selected for programming. Thefollowing equation determines an amount of current passing throughtransistor M0 303 and applying to fuse 601 during the programming mode:

(V _(WVVD) −V _(VGSP) _(—) _(CORE))/R=n*I _(M0)  (2)

[0126] wherein V_(WVVD) is the voltage at the power supply terminal 211,V_(VGSP) _(—) _(CORE) is the bias voltage of transistor M7 312, R is avalue of resistance R 314, and n is a constant that depends on the valueof resistance R. In an embodiment, resistance R varies, according to thesize and length of a connector connecting ground WVSS 212 and transistorM7 312.

[0127] When fuse 601 is selected for programming, transistor M5 315turns on connecting signal VDRIVE 213 to the gate of transistor M0 303.As a result, transistor M0 303 turns on. Because VDRIVE 213 is connectedto the gate of M0 303, VDRIVE 213 applies a constant amount of voltageto the gate of M0 303. This way PMOS diode 210 controls the amount ofcurrent that flows through transistor M0 303 and to the fuse 601.Because of the current mirror configuration, the amount of current thatflows through transistor M7 312 equals to the amount of current thatflows through transistor M0 303 . The value of resistance R 314 controlsthe amount of current that flows through transistor M7 312.

[0128] Using PMOS diode 210 and current mirror configuration oftransistors M7 312 and M0 303, fuse 601 can be programmed tohigh-resistance without a danger of fuse's poly-silicon/silicide layerre-flowing back to its original configuration. Application of optimalcurrent I_(M0) melts fuse 601 polysilicon/silicide layer in the center,which creates an open circuit in the polysilicon/silicide layer of fuse601.

[0129] As would be understood by one having ordinary skill in the art,current I_(M0) can be adjusted to different levels in order to give ahighest programming yield. Furthermore, the PMOS diode 210 configurationis shared among different memory cells within row-column matrix of fusearray 230 (not shown in FIG. 3b)

[0130] In an example embodiment, such constant current programmingprovides high repeatability and reliability as compared to conventionalvoltage based programming. The conventional voltage based programmingrequires high voltages (>2.5V), which are incompatible with sub-micronCMOS technology. Programming in accordance with the present invention isless susceptible to electrostatic discharge damage of the fuse via powersupply terminal WVDD 211.

[0131] The following is a description of a method of current applicationto fuse 601 during the programming mode. FIG. 3c is a flowchart diagramof a method 370 describing application of current to fuse 601.

[0132] In step 371, system 310 applies current to first transistor M7312 in the current mirror configuration. The current is applied frompower supply terminal WVDD 211 and ground WVSS 212. Transistor M7 312 isbiased using voltage VGSP_CORE 313. This allows for a controlledapplication of current for transistor M7 312 through resistance R 314.

[0133] In step 372, once the current is applied to transistor M7 312, itgenerates a voltage signal VDRIVE 213. Signals COL 241 and WRITE_ROW 242turn on transistor M5 315, if fuse 601 is selected for programming. Thisallows for the voltage bias from VDRIVE 213 to be applied directly to agate of transistor M0 303. By applying current to the gate of transistorM0 303, the transistor M0 303 turns on to allow a proportional currentto flow to fuse 601, which is coupled to transistor M0 303.

[0134] In step 373, system 210 controls an amount of current flowingthrough transistor M7 312. The amount of current flowing throughtransistor M7 312 is controlled by varying resistance R 314. ResistanceR 314 is coupled between the power supply terminal 211 and ground 212and transistor M7 312. Therefore, the current that flows throughtransistor M7 312 is determined using equation (2) above.

[0135] The processing proceeds to step 374. In step 374, because of thecurrent mirror configuration, the amount of current that flows throughtransistor M0 303 is controlled by the amount of current that flowsthrough transistor M7 312. In other words, the current flowing throughtransistor M0 303 is determined using equation (2) above, as well.

[0136] In step 375, the current flowing through transistor M0 303applies to fuse 601 over time. This method allows for a continuous andcontrolled application of current to fuse 601.

[0137] 3. OTP Memory Element in—System Operation.

[0138] There are several modes of operation of OTP element memory core120 in the present invention. These are programming, reading andverification modes. In the programming mode, the system identifies amemory cell for programming and programs it. During the programmingmode, the fuse contained in the identified memory cell is blown orfused. In other words, selected memory cell changes its state from lowresistance to high resistance.

[0139] After the fuse is programmed, the system can go into theverification mode. In an embodiment, the system can automatically switchto the verification mode. In an alternative embodiment, a user canswitch the system into the verification mode. In the verification mode,the system determines whether the fuse in the selected memory cell wasprogrammed or not. The system's components involved in the verificationmode apply current to the fuse to generate a fuse voltage.

[0140] In an embodiment, a user can switch the system to theverification mode. In an alternative embodiment, the system canautomatically switch to the verification mode immediately after a fuseis programmed during the programming mode. In the verification mode, thesystem performs a comparison between fuse voltage and minimum andmaximum threshold voltages. The maximum threshold voltage serves whenverifying an unprogrammed fuse. Whereas, the minimum threshold voltageserves when verifying a programmed fuse. The minimum and maximumthreshold voltages are determined by the system or the user.Verification mode's purpose is to guarantee quality of the fuse selectedfor programming, as well as, guarantee that the fuse is properlyprogrammed.

[0141] The verification mode involves the verification circuit. Theverification circuit compares the voltage applied to fuse in theselected memory cell to a threshold voltage generated by theverification voltage. Upon voltage comparison, the verification circuitensures reliable programming of the fuse.

[0142] Reading mode is a mode where a user retrieves memory contents ofthe selected cell or cells. This operation is typically, but notnecessarily exclusively, performed by an end-user of the OTP elementmemory core 120 after the OTP element memory core 120 has beenprogrammed and verified during programming and verification modes,respectively.

[0143] After OTP element memory core 120 completes programming, readingand verification modes of the identified memory cell, the OTP elementmemory core 120 may proceed to identify another memory cell. The newlyidentified memory cell will be subject to programming, reading and/orverification modes as desired by the user and/or OTP element memory core120.

[0144] A more detailed description of programming mode, reading mode,and verification mode follows. As would be understood by one skilled inthe relevant art, other embodiments of each mode or combination of modesis possible to achieve reliable programming of the fuse, thus, thepresent invention is not limited to the embodiments described below.

[0145] a. Programming Mode.

[0146] FIGS. 9(a, b, c, d) illustrate method 900 of operation of OTPelement memory core 120 in the programming mode. FIG. 9a illustratesgeneral steps of the method 900. FIGS. 9b, 9 c, and 9 d illustratesdetails of particular steps of method 900 shown in FIG. 9a.

[0147]FIG. 9a illustrates method 900 for programming a memory cell 601in the fuse array 230. In step 910, OTP element memory core 120 receivesan input signal from digital interface 130. The input signal includes aCLK signal 275 that drives internal timing generator 270. The inputsignal further includes input address signal 245 that drives addressdecoder 240. As a result, internal timing generator 270 generatessignals ROW_CLK signal 271, COL_CLK signal 272 and ADDR_CLK signal 273.

[0148] The processing then proceeds to step 920, where OTP elementmemory core 120 selects a memory cell 601 within fuse array 230 forprogramming. Step 920 is further described by FIG. 9b.

[0149] Referring to FIG. 9b, in step 921, address decoder 240 receives8-bit input address signal 245 from digital interface 130. 8-bit inputaddress signal 245, when decoded by address decoder 240, defines amemory cell 601 within fuse array 230.

[0150] In step 922, address decoder 240 also receives signals ROW_CLK271, COL_CLK 272 and ADDR_CLK 273. In an embodiment, memory cells 601 offuse array 230 are in a row-column matrix arrangement, as shown in FIG.6. Therefore, ROW_CLK 271, COL_CLK 272 and ADDR_CLK 273 define a memorycell 601 within fuse array 230 row-column matrix.

[0151] In step 923, address decoder 240 decodes ROW_CLK 271, COL_CLK 272and ADDR_CLK 273 and 8-bit input address signal 245 into COL signal 241and WRITE_ROW signal 242. COL signal 241 defines a particular column inthe row-column matrix arrangement of fuse array 230 where memory cell601 selected for programming is located. WRITE_ROW signal 242 defines aparticular row in the row-column matrix arrangement of fuse array 230where memory cell 601 selected for programming is located. COL signal241 and WRITE_ROW signal 242 are generated based on the informationsupplied by ROW_CLK 275 and COL_CLK 272 signals. The processing proceedsto step 924, where memory cell 601 within row-column matrix arrangementoff use array 230 is selected.

[0152] Referring back to FIG. 9a, in step 930, the OTP element memorycore 120 initiates programming of the selected memory cell 601. Theprogramming begins with a receipt of ADDR_CLK 273 by OTP element memorycore 120.

[0153] The selected memory cell 601 in fuse array 230 can be verifiedbefore the programming mode 900 starts. Referring to FIG. 9c, in step931 a user can initiate a verification mode to verify the “good quality”unprogrammed memory cells 601. If the selected memory cell 601 is a“good quality” memory cell 601, then the user proceeds with verifyingmemory cell 601, as shown in step 933. If selected memory cell 601 isnot “good quality” memory cell, then the user designates the cell as nothaving “good quality” and does not proceed with programming, as shown instep 934. This process can be performed before OTP element memory core120 is delivered to a potential customer or an end-user.

[0154] OTP element memory core 120 performs verification of memory cell601 during the programming mode using a digital sequencer 280 (as shownin FIG. 2). Digital sequencer 280 times the actual programming of thememory cell and verification of memory cell 601 during the programmingmode. Digital sequencer 280 ensures that ample time is given for eachthe programming and verification to complete before allowing for thenext one begins.

[0155] Referring back to FIG. 9a, after the programming mode isinitiated, the processing proceeds to step 940. In step 940, aprogramming current is applied to selected memory cell 601.

[0156]FIG. 9d further describes step 940. In step 941, PMOS diode 210generates a constant amount of current and applies it to memory cell601. The current is applied using PMOS diode 210 configuration (asdescribed in FIG. 3b). PMOS diode 210 applies the constant amount ofcurrent to memory cell 601 over a time period, as indicated by step 942.Using a current mirror configuration of its transistors, PMOS diode 210controls the amount current that passes through selected memory cell601. This ensures that the current applied evenly over time. This isdifferent from conventional systems, where current applies in massivedosages melting the poly-silicon layer of the fuse causing the moltenpoly-silicon to re-flow back into original configuration.

[0157] Referring back to FIG. 9a, in step 950, OTP element memory core120 finishes programming mode. OTP element memory core 120 also verifiesthat programmed memory cell 601 is a good memory cell. This is referredto as a post-verify event. This even verifies that the programmed memorycell 601 is programmed to high resistance. Digital sequencer 280switches OTP element memory core 120 from the actual programming part ofthe programming mode to the verification part of the programming mode.After verification is completed, the digital sequencer 280 issues asignal indicating completion of the programming mode.

[0158] During the entire programming mode, the verification modeoptionally runs in the background to make sure that the fuse selectedfor programming is a valid good fuse. After the programming mode isover, digital sequencer 280 disengages. The user switches OTP elementcore 120 to reading mode for read-back and optionally to verificationmode, if further verification is desired.

[0159] After the programming mode, the system or the user can switch OTPelement memory core 120 to the reading mode. The reading mode isdescribed in below in detail.

[0160]FIG. 9e is a flowchart diagram illustrating a sequence ofprocesses 980 including a process at a manufacturer's site 971, aprocess at a customer's site 972, and a process at an end-user's site973.

[0161] The process at the manufacturer's site 971 includes averification mode 971 a, a programming mode to program a test row and acolumn 971 b, a step of rejecting bad parts (i.e., memory cells 601qualified as not having “good quality”) 971 c, and a step of deliveringgood parts (i.e., memory cells 601 qualified as having “good quality”)to customer 971 d.

[0162] The process at the customer's site 972 includes a pre-programmingverification mode 972 a, followed by a programming mode 972 b, and areading mode 972 c to determine contents of a memory cell.

[0163] The process at the end-user's site 973 includes a reading mode973 a.

[0164] As would be understood by one having ordinary skill in the art,other systems and methods for programming a memory cell are possible aslong as they are within the scope and spirit of the present invention.

[0165] b. Reading Mode.

[0166]FIGS. 12a and 12 b describe a method 1200 of operation of OTPelement memory core 120 during the reading mode. FIG. 12a describesgeneral steps performed by OTP element memory core 120 during thereading mode. FIG. 12b describes further details of one of the steps ofmethod 1200 of FIG. 12a.

[0167]FIG. 12a illustrates method 1200 where OTP element memory core 120determines whether a selected memory cell 601 is programmed orunprogrammed. During the reading mode, OTP element memory core 120utilizes current reference generator 220, verification circuits 260 andsense amplifier 250.

[0168] In step 1210, the OTP element memory cell 120 selects a memorycell 601 for reading using COL 241 and WRITE_ROW 242 signals (as shownin FIGS. 2 and 3b). COL 241 and WRITE ROW 242 are the same signals usedto select a memory cell 601 for programming.

[0169] The processing proceeds to step 1220, where current referencegenerator 220 provides IFEED current signal 222 to the selected memorycell 601 within fuse array 230. Upon application of current to theselected memory cell 601, a fuse voltage is generated. The fuse voltageis monitored by sense amplifier 250 via RDLINE signal line 231.

[0170] In step 1230, OTP element memory core 120 generates a readingthreshold voltage VT_READ 1113 (as shown in FIG. 11). Reading thresholdvoltage VT_READ 1113 is compared to the fuse voltage generated in step1220. FIG. 12b illustrates a method for generating reading thresholdvoltage VT_READ 1113.

[0171] Referring to FIGS. 10, 11 and 12 b, in step 1231, verificationcircuit 260 generates READ_VREF signal 1013 based on the signalssupplied to it from OTP element memory core 120.

[0172] In step 1232, READ_VREF signal 1013 is applied to transistorswitch 1007, which closes transistor switch 1007.

[0173] In step 1233, voltage VT_READ 1032 is provided at terminalVREF_OUT 264 of verification circuit 260, as a result of transistorswitch 1007 closing.

[0174] Referring back to FIG. 12a, in step 1240, OTP element memory core120 compares the fuse voltage, generated in step 1220, and VT_READ 1032,generated in step 1230.

[0175] If, in decision step 1250, the fuse voltage is greater thanVT_READ 1032, then selected memory cell 601 is read as programmed(corresponding to logical ‘1’) (step 1260). If the fuse voltage is lessthan VT_READ 1032, then selected memory cell 601 is read as unprogrammed(that is logical ‘0’). OTP element memory core 120 uses sense amplifier250 to compare the voltages. Sense amplifiers 250, via RDLINE signalline 231, monitors the fuse voltage (as shown in FIG. 10). If the fusevoltage is greater than VT_READ 1032, sense amplifier 250 generates asignal indicating that selected memory cell 601 is programmed.

[0176] In an embodiment, sense amplifier 250 includes a folded-cascadestage cascaded with a NMOSFET that is biased in class-A configuration,as shown in FIG. 15. The folded cascade stage is designed using largeinput transistors. Furthermore, sense amplifier 250 uses long-lengthtransistors in current mirrors to minimize offsets. Other embodiments ofsense amplifier 250 are possible.

[0177] In an embodiment, OTP element memory core 120 can initiate averification mode after the reading mode is over. In another embodiment,a user can initiate the verification mode. The verification mode ensuresthat the programming of the selected memory cell 601 was done correctlyor it can be used to verify the unprogrammed status of the cell 601.During the verification mode, OTP element memory core 120 comparesselected memory cell 601 fuse voltage against thresholds generated bythe system. The following is a detailed description of a method ofoperation of OTP element memory core 120 during the verification mode.

[0178] c. Verification mode.

[0179]FIGS. 13a-d illustrate a method of operation of OTP element memorycore 120 during the verification mode. FIG. 13a illustrates steps of themethod of operation 1300 during a pre-programming verification mode.FIG. 13b illustrates steps of the method of operation 1302 during apost-programming verification mode. FIG. 13c illustrates details of oneof the steps of method 1300 shown in FIG. 13a. FIG. 13d illustratesdetails of one of the steps of method 1302 shown in FIG. 13b.

[0180] Referring to FIG. 13a, in step 1305, OTP element memory core 120initiates a pre-programming verification mode of the selected memorycell 601. The pre-programming verification mode ensures that theselected memory cell 601 is a “good quality” memory cell. In otherwords, that the fuse voltage of memory cell 601 is below a definedthreshold voltage.

[0181] In step 1310, OTP element memory core 120 generates thepre-programming verification threshold voltage V_(threshp) 1114. In step1311 (FIG. 13c), verification circuit 260 generates VERIFY_PREBLOWNcurrent 1014 based on signals received from OTP element memory core 120.In step 1312, VERIFY_PREBLOWN current 1014 is applied to transistorswitch 1008, which closes transistor switch 1008. In step 1313, voltageV_(threshp) 1114 is provided at output terminal 264 of the verificationcircuit 260 through the transistor switch 1008.

[0182] Referring back to FIG. 13a, in step 1315, current IFEED 222 fromcurrent reference generator 220 is applied to a selected memory cell601. Because memory cell 601 is not programmed, it has a low resistance.Therefore, a low fuse voltage is generated upon application of IFEEDcurrent 222 to selected memory cell 601.

[0183] In step 1320, the low fuse voltage is monitored by RDLINE signalline 231. RDLINE signal line 231 supplies the low fuse voltage to senseamplifier 250 for comparison with V_(threshp) voltage 1114. Thethreshold voltage 1114 is lower than the reading threshold voltage toensure verification of the unprogrammed fuse.

[0184] In step 1325, sense amplifier 250 compares V_(threshp) voltage1114 and the low fuse voltage as monitored by RDLINE 231. The processingproceeds to decision step 1330. In step 1330, sense amplifier 250determines whether the fuse voltage on RDLINE 231 (V_(RDLINE)) is lessthan the threshold voltage V_(threshp) 1114. If sense amplifier 250determines that V_(RDLINE) is less than V_(threshp) then processingproceeds to step 1345.

[0185] In step 1345, sense amplifier 250 generates a signal that theselected memory cell 601 is a “good quality” memory cell. This meansthat upon application of current to the memory cell 601, a low fusevoltage is generated that is less than a threshold voltage 1114. In step1350, the user can then proceed to the programming mode, described inFIGS. 9a-d.

[0186] If in decision step 1330, threshold voltage 1114 is not less thanthe fuse voltage as monitored by RDLINE 231, then sense amplifier 250generates a signal indicating that selected memory cell 601 is not a“good quality” memory cell. Therefore, in step 1350, OTP element memorycore 120 is prompted to select another memory cell.

[0187] After programming, the system switches to a post-programmingverification mode. This mode verifies that the programmed memory cell601 was programmed and that upon application of a current it generates ahigh programming voltage. The high programming voltage results fromapplication of current to programmed memory cell having high resistance.

[0188]FIGS. 13b and 13 d describe the post-programming verificationmode. FIG. 13b illustrates steps of the method of operation 1302 duringa post-programming verification mode. FIG. 13d illustrates details ofone of the steps of method 1302 shown in FIG. 13b.

[0189] Referring to FIG. 13b, in step 1355, OTP element memory core 120initiates a post-programming verification mode of the programmed memorycell 601. The post-programming verification mode ensures that theprogrammed memory cell 601 is properly programmed.

[0190] In step 1360, OTP element memory core 120 generates thepost-programming verification threshold voltage V_(threshb) 1112. Instep 1361, verification circuit 260 (FIG. 13d) generates VERIFY_BLOWNcurrent 1012 based on signals received from OTP element memory core 120.In step 1362, VERIFY_BLOWN current 1012 is applied to transistor switch1006, which closes transistor switch 1006. In step 1363, voltageV_(threshb) 1112 is provided at output terminal 264 of the verificationcircuit 260 through the transistor switch 1006.

[0191] Referring back to FIG. 13b, in step 1365, current IFEED 222 fromcurrent reference generator 220 is applied to programmed memory cell601. Because memory cell 601 is programmed, it has a high resistance.Therefore, a high fuse voltage is generated upon application of IFEEDcurrent 222 to programmed memory cell 601.

[0192] In step 1370, the high fuse voltage is monitored by RDLINE signalline 231. RDLINE signal line 231 supplies the high fuse voltage senseamplifier 250 for comparison with V_(threshb) voltage 1112. Thethreshold voltage 1112 is purposefully skewed to provide for a highestpossible threshold voltage.

[0193] In step 1375, sense amplifier 250 compares V_(threshb) voltage1112 and the high fuse voltage as monitored by RDLINE 231. Theprocessing proceeds to decision step 1380. In step 1380, sense amplifier250 determines whether fuse voltage determined by RDLINE 231(V_(RDLINE)) is greater than threshold voltage V_(threshb) 1112. Ifsense amplifier 250 determines that V_(RDLINE) is greater thanV_(threshb) then processing proceeds to step 1395.

[0194] In step 1395, sense amplifier 250 generates a signal that theprogrammed memory cell 601 is properly programmed. This means that uponapplication of current to programmed memory cell 601, a high fusevoltage is generated that is greater than threshold voltage 1112.

[0195] If in decision step 1380, threshold voltage 1112 is not greaterthan the fuse voltage as monitored by RDLINE 231, then sense amplifier250 generates a signal indicating that programmed memory cell 601 is notproperly programmed. In other words, fuse voltage of memory cell 601 isless than the highest threshold voltage. Therefore, in step 1390, OTPelement memory core 120 is prompted to select another memory cell fromfuse array 230 and re-initiate the programming mode.

[0196]FIG. 13e is a process flowchart for independent initiation ofverification mode 1301 a. In step 1302 a, verification mode 1301 abegins by selecting memory cell 601 in fuse array 230 and applying acurrent to the selected memory cell 601 to generate RDLINE signal 231.The processing proceeds to step 1303 a.

[0197] In step 1303 a, digital bits representing digital input signal DI261 are inputted to verification circuits 260. The digital bit hasvalues of either ‘0’ or ‘1’, where ‘0’ indicates absence of current and‘1’ indicates presence of current.

[0198] In decision step 1304 a, if a digital bit of digital input signalDI 261 has a value of ‘1’, then processing proceeds to step 1305 a.

[0199] In step 1305 a, voltage signal V_(threshb) 1112 is compared toRDLINE signal 231, as shown in step 1316 a. If V_(threshb) 1112<RDLINEsignal 231, then the selected memory cell 601 is a “good quality” memorycell, as shown in step 1306 a. The process then proceeds to step 1307 ato select another memory cell 601 for verification.

[0200] If in step 1305 a, V_(threshb) 1112<RDLINE signal 231, thenselected memory cell 601 is not a “good quality” memory cell, as shownin step 1308 a. A signal is sent to digital interface 130 indicatingthat selected memory cell 601 is not a “good quality” memory cell, asshown in step 1315 a. The processing then proceeds to step 1307 a toselect another memory cell for verification.

[0201] If in decision step 1304 a the digital bit of digital inputsignal DI 261 has a value of ‘0’, then processing proceeds to step 1309a. In step 1309 a, voltage signal V_(threshp) 1114 is compared to RDLINEsignal 231.

[0202] Referring to step 1310 a, if V_(threshp) 1112>RDLINE signal 231,then the selected memory cell is verified as a “good quality” memorycell, as shown in FIG. 1311a. The processing then proceeds to step 1307a, where another memory cell is selected for verification.

[0203] If in step 1310 a V_(threshp) 1112<RDLINE signal 231, then theselected memory cell 601 is verified as not having “good quality”, asshown in step 1312 a. A signal is sent to digital interface 130indicating that the selected memory cell 601 does not have “goodquality”, as shown in step 1313 a. The processing then proceeds to step1307 a, where another memory cell is selected for verification.

[0204] 4. Poly-Si Fuse Design.

[0205]FIGS. 14a-d illustrate a one-time programmable fuse 1400 inaccordance with the present invention. FIG. 14a illustrates a top viewof the one-time programmable fuse 1400. FIG. 14b illustrates a top viewof a practical implementation of one-time programmable fuse 1400. FIG.14c is a cross-sectional view of an unprogrammed fuse 1400 shown in FIG.14b. FIG. 14d FIG. 14c is a cross-sectional view of a programmed fuse1400 shown in FIG. 14b. The following is a description of the designsshown in FIGS. 14a-d. Further details of the one-time programmable fuse1400 can be found in U.S. patent application Ser. No. 10/115,013, toAkira et al., filed Apr. 4, 2002, which is incorporated by referenceherein in its entirety.

[0206]FIG. 14a illustrates a polycide fuse 1400 having an N+implantationregion 1401, a P+implantation region 1402 and a poly-silicon layer 1450.The implant regions 1401 and 1402 are drawn over the poly-silicon layer1450.

[0207] During the fabrication process of the polycide fuse 1400,N+implantation region 1401 and P+implantation region 1402 typicallyoverlap, forming a third region 1403, as shown in FIG. 14b. This thirdregion is referred to as an intrinsic region (or neutral region).Intrinsic region 1403 is a region of poly-silicon that is nether P+dopednor N+doped. In an embodiment, intrinsic region 1403 is formed by anoverlap of P+implantation region 1402 and N+implantation region 1401. Inanother embodiment, intrinsic region 1403 is formed by defining animplantation blocking region. The three regions 1401, 1402 and 1403 havedifferent sheet resistances with the intrinsic region 1403 having thehighest sheet resistance. The silicide layer 1415 is similarly affectedby the above described implantation process as the polysilicon layer1450.

[0208]FIGS. 14c and 14 d illustrate a cross sectional view of thepolycide fuse 1400 of FIG. 14b. Polycide fuse 1400 includes a polyamidelayer 1410, metal layer 1414, oxide layers 1412 and 1413, a silicidelayer 1415, a poly-silicon layer 1416 with the intrinsic region 1403 aand an oxide layer 1417. FIG. 14d illustrates a cross-section view of aprogrammed fuse 1400, where a void window 1420 is created in thepoly-silicon layer 1416.

[0209] The structural details of fuse 1400 are described in U.S. patentapplication Ser. No. 10/115,013, to Akira et al., filed Apr. 4, 2002,which is incorporated by reference herein in its entirety.

[0210] As would be understood by one having ordinary skill in the art,the fusing performance of a fuse depends on a number of factors such asprogramming current, programming time, fuse size, fuse shape, silicideand poly-silicon quality. The better fusing performance in the newtri-region polycide fuses is due to the better quality silicide linesthat are formed on tri-region polysilicon layer, FIG. 14b, as comparedto other types of doped polysilicon. The presence of the silicide layer1415 acts as a smaller resistance in parallel with the poly-siliconlayer 1416 to form a fuse resistance that is much smaller than apolysilicon fuse without silicide. A higher-quality silicide line willensure better fusing success rate statistically.

[0211] Due to the tri-region arrangement in fuse 1400, when theprogramming current is injected into the fuse, more heat is generated inintrinsic region 1403. Intrinsic region 1403 is specially located in aregion where the layers are more even and this region is situated at thecenter of the fuse, away from the uneven end regions of the fuse, asshown in FIGS. 14b-d. This improves the chance of the silicide meltingat the fuse center and for the silicide strip to retreat more easilyinto two separate equal parts from the center.

[0212] 5. Conclusion.

[0213] Example embodiments of the methods, systems, and components ofthe present invention have been described herein. As noted elsewhere,these example embodiments have been described for illustrative purposesonly, and are not limiting. Other embodiments are possible and arecovered by the invention. Such embodiments will be apparent to personsskilled in the relevant art(s) based on the teachings contained herein.Thus, the breadth and scope of the present invention should not belimited by any of the above-described exemplary embodiments, but shouldbe defined only in accordance with the following claims and theirequivalents.

What is claimed is:
 1. A method for ensuring quality of an one-timeprogrammable memory cell, wherein when a current is applied toprogrammed and unprogrammed memory cell a voltage is generated, wherebywhen a memory cell is programmed, the generated voltage is higher than afirst reference voltage, whereby when the memory cell is unprogrammed,the generated voltage is lower than a second reference voltage,comprising: (1) programming a memory cell within an array of memorycells; (2) applying a current to the programmed memory cell, therebygenerating the voltage for the programmed memory cell; (3) comparing thegenerated voltage for the programmed memory cell to a first thresholdvoltage; (4) declaring programmed memory cell verified when thecorresponding generated voltage is higher than the first thresholdvoltage; (5) applying the current to un-programmed memory cell, therebygenerating the voltage for the un-programmed memory cell; (6) comparingthe generated voltage of the un-programmed memory cell to a secondthreshold voltage; (7) declaring un-programmed memory cell verified whenthe corresponding generated voltage is lower than the second thresholdvoltage; and (8) reading the memory cell using a reading referencevoltage.
 2. The method according to claim 1, wherein step (8) comprises:(a) comparing the generated voltage for a selected memory cell to thereading reference voltage; (b) declaring the selected fuse programmedwhen the generated voltage is higher than the reading reference voltage;and (c) declaring the selected fuse un-programmed when the generatedvoltage is lower than the reading reference voltage.
 3. A method forverifying programming of fuses, wherein when a current is applied to aprogrammed fuse a first voltage is generated that is lower than areference voltage, wherein when the current is applied to anunprogrammed fuse, a second voltage is generated that is higher than thereference voltage, comprising: (1) programming one or more fuses withinan array of fuses, (2) generating a verify-programmed voltage that ishigher than the reference voltage; (3) generating a verify-unprogrammedvoltage that is lower than the reference voltage; (4) applying thecurrent to programmed fuses in the array, thereby generating the firstvoltage for each of the programmed fuses; (5) comparing theverify-programmed voltage to the first voltage generated for each of theprogrammed fuses; (6) declaring programmed fuses failed when thecorresponding first voltage is lower than the verify-programmed voltage;(7) declaring programmed fuses verified when the corresponding firstvoltage is higher than the verify-programmed voltage; (8) applying thecurrent to unprogrammed fuses in the array, thereby generating thesecond voltage for each of the unprogrammed fuses; (9) comparing theverify-unprogrammed voltage to the second voltage generated for each ofthe unprogrammed fuses; (10) declaring unprogrammed fuses failed whenthe corresponding second voltage is higher than the verify-unprogrammedvoltage; and (11) declaring unprogrammed fuses verified when thecorresponding second voltage is lower than the verify-unprogrammedvoltage.
 4. A method for verifying programming of fuses, wherein when acurrent is applied to programmed and unprogrammed fuses a voltage isgenerated, whereby when a fuse is programmed, the generated voltage ishigher than a reference voltage, whereby when the fuse is unprogrammed,the generated voltage is lower than the reference voltage, comprising:(1) programming one or more fuses within an array of fuses, (2) applyingthe current to a selected one of the fuses, thereby generating thevoltage for the selected fuse; (3) comparing the generated voltage forthe selected fuse to a first threshold voltage that is lower than thereference voltage and to a second threshold voltage that is higher thanthe reference voltage; (4) verifying the selected fuse as programmedwhen the generated voltage is higher than the first threshold voltage;and (5) verifying the selected fuse as un-programmed when the generatedvoltage is lower than the second threshold voltage.
 5. A system forproviding a one-time programmable memory, comprising: a digitalinterface; a one-time programmable memory element, wherein said digitalinterface provides a plurality of input reference signals to saidone-time programmable memory element; wherein said one-time programmablememory element further comprises: a plurality of one-time programmablefuses; an internal timing generator capable of generating a plurality ofaddress signals; an address decoder, wherein said address decoder andsaid internal timing generator select and program a first fuse out ofsaid plurality of one-time programmable fuses based on said plurality ofaddress signals and said input reference signals; a current referencegenerator capable of generating a read signal to determine whether saidfirst fuse is programmed; a means for verifying whether said first fuseselected based on said plurality of address signals is properlyprogrammed.
 6. The system of claim 5, wherein said plurality of one-timeprogrammable fuses is arranged in a row-column matrix arrangement. 7.The system of claim 6, wherein said plurality of address signals definea row location and a column location of said first fuse to be programmedwithin said row-column matrix.
 8. The system of claim 6, wherein saidrow-column matrix further comprises eight rows of 32-bit columns.
 9. Thesystem of claim 5, wherein said read signal is supplied to said firstfuse after said first fuse was programmed, wherein said read signal iscompared against a threshold voltage generated by said verifying means.10. The system of claim 5, wherein verifying means detect whether saidfirst fuse is pre-programmed, un-programmable and post-programmed. 11.The system of claim 10, wherein said verifying means apply a current tosaid first fuse to generate a pre-programming voltage, wherein saidfirst fuse is pre-programmed when said pre-programming voltage is lessthan a pre-programming threshold voltage generated by said verifyingmeans.
 12. The system of claim 11, wherein said first fuse ispre-programmed when it provides high resistance to the current appliedto said first fuse.
 13. The system of claim 10, wherein said verifyingmeans apply a current to said first fuse to generate a post-programmingvoltage, wherein said first fuse is post-programmed when saidpost-programming voltage is greater than a post-programming thresholdvoltage generated by said verifying means.
 14. The system of claim 13,wherein said first fuse is post-programmed when it provides lowresistance to the current applied to said first fuse.
 15. The system ofclaim 10, wherein said verifying means apply a current to said firstfuse to generate a verifying voltage, wherein said first fuse isun-programmable when said verifying voltage is less than apost-programming threshold voltage generated by said verifying means andgreater than a pre-programmed threshold voltage generated by saidverifying means.
 16. The system of claim 5, further comprising a currentsupply circuit, wherein said current circuit generates a constant amountof current and supplies said constant amount of current to said firstfuse.
 17. A method for programming a one-time programmable memoryelement coupled to a digital interface, wherein the one-timeprogrammable memory element has an internal timing generator, an addressdecoder, a current reference generator and a verification circuit,comprising the steps of: (a) receiving an input address signal by theone-time programmable memory element from the digital interface; (b)receiving a timing signal by the address decoder from the internaltiming generator; (c) selecting a fuse for programming using the inputaddress signal and the timing signal; (d) programming the fuse; (e)determining whether the fuse is programmed, wherein said determiningfurther comprising: applying a current to the fuse; generate a readingvoltage, wherein the fuse is programmed when the reading voltage matchesa reading threshold voltage generated by the verification circuit; and(f) verifying whether the fuse is programmable, wherein said verifyingfurther comprising: applying a current to the fuse; generating averifying voltage to determine whether the fuse is pre-programmed,un-programmable and post-programmed.
 18. The method of claim 17, whereinsaid step (f) further comprises: applying a current to the fuse;generating a pre-programming voltage, wherein the fuse is pre-programmedwhen the pre-programming voltage is less than a pre-programmingthreshold voltage generated by the verification circuit.
 19. The methodof claim 17, wherein said step (f) further comprises: applying a currentto the fuse; generating a post-programming voltage, wherein the fuse ispost-programmed when the post-programming voltage is greater than apost-programming threshold voltage generated by the verificationcircuit.
 20. The method of claim 17, wherein said step (f) furthercomprises: applying a current to the fuse; generating the verifyingvoltage, wherein the fuse is un-programmable when the verifying voltageis less than a post-programming threshold voltage generated by theverification circuit and greater than a pre-programmed threshold voltagegenerated by the verification circuit.
 21. The method of claim 17,wherein said step (d) further comprises applying a constant amount ofcurrent to the fuse.